Modern electronic devices, especially semiconductor (SC) devices and integrated circuits (ICs) are at risk of damage due to electrostatic discharge (ESD) events. It is well known that electrostatic discharge from handling SC devices and ICs, by humans or machines or both, is a source of such excess voltage. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input/output (I/O) and other terminals of such SC devices and IC's.
FIG. 1 is a simplified schematic diagram of circuit 10 wherein ESD clamp 11 is placed between input/output (I/O) terminals 22 and ground or common terminal 23 of a SC device or IC to protect the other devices on the chip, that is, to protect circuit core 24 which is also coupled to I/O terminals 22 and common (e.g., “GND”) terminal 23. Zener diode symbol 111 within ESD clamp 11 indicates that the function of ESD clamp 11 is to limit the voltage than can appear across circuit core 24 irrespective of the voltage applied to external I/O and GND terminals 22, 23. It is not intended to imply that a Zener diode is actually employed in ESD clamp 11. As used herein, the abbreviation “GND” is intended to refer to the common or reference terminal of a particular circuit or electronic element, irrespective of whether it is actually coupled to an earth return and the abbreviation “I/O” is intended to include any external terminal other than “GND”.
FIG. 2 is a simplified schematic diagram illustrating internal components of prior art gate-coupled N-channel metal-oxide-semiconductor (NMOS) ESD clamp 21 that is inserted in circuit 10 in place of ESD clamp 11 and FIG. 3 is a simplified combined schematic and cross-sectional view through clamp 21 as typically implemented in semiconductor substrate 20. ESD clamp 21 comprises parasitic NPN lateral bipolar transistor 25, having emitter 26, collector 27 and base 28, and NMOS transistor 30 with source 31, drain 32 and gate 33. Parasitic gate-drain capacitance Cgd 34, gate-source resistor 35 and bulk-source resistor Rbs 36 are also shown. Avalanche current source 37 is effectively coupled between collector 27 and base 28 of bipolar transistor 25. As shown in FIG. 3, semiconductor substrate 20 comprises PWELL 40 wherein N+ region 41 therein acts as source 31 and parasitic emitter 26, and N+ region 42 therein acts as drain 32 and parasitic collector 27. Avalanche current source 37 is coupled between collector region 27, 42 and base 28 of bipolar transistor 25 provided by PWELL 40. Channel region 44 of PWELL 40 contains the channel of NMOS 30. P+ contact region 46 is coupled via PWELL 40 to base 28 of parasitic bipolar transistor 25 and the body of NMOS transistor 30 in which channel region 44 conducts under appropriate bias. When an ESD transient appears between I/O 22 and GND 23, ESD clamp 21 turns on to harmlessly divert the ESD transient. FIG. 4 illustrates current-voltage plot 50 of an ESD clamp, wherein trace 52 shows the general behavior of typical prior art ESD clamp 21. When a positive voltage is applied between I/O 22 and GND 23, negligible current flows until “trigger voltage” Vt1 is reached, whereupon ESD clamp 21 turns on. Once current begins to flow, the voltage between I/O 22 and GND 23 drops to what is called the “holding voltage” Vh, generally substantially less than trigger voltage Vt1 and the current rises rapidly to whatever saturation value is determined, for example, by the internal impedance of the ESD voltage source. The voltage difference between Vt1 and Vh is referred to as the “snap-back”, indicated by voltage difference 53.
While prior art ESD clamps such as ESD clamp 21, can perform the above-described protection function well, they can also suffer from a number of undesirable limitations. A particularly serious difficulty can rise when such ESD protection elements are used in SC devices and ICs fabricated with deep submicron manufacturing processes often associated with very high speed digital and analog applications. With such manufacturing processes, the threshold voltage of NMOS device 30 may be very low, for example, ˜0.3 volts or less, while I/O 22 to which it is coupled may experience non-ESD operating signals as high as, for example, a volt or more. These operating signals can be significantly larger than the threshold voltage of device 30 but much less than voltages of concern from ESD events. Ordinarily, ESD clamp 21 should ignore such (non-ESD) operating signals appearing at I/O 22. These (non-ESD) operating signal appearing at I/O 22 can be coupled to gate 33 via parasitic gate-drain capacitance Cgd. For low operating speeds (e.g., low dv/dt), this causes no significant rise in gate voltage unless the much larger voltage associated with an ESD event is experienced, in which case the ESD clamp behaves as intended. However, as the operating speed of the associated devices or ICs rises, the increased dv/dt of the ordinary (non-ESD) signal appearing on I/O 22 can cause the voltage appearing on gate 33 to rise above the threshold voltage, causing ESD clamp 20 to turn ON in response to the rapid I/O signal condition rather than an ESD event. Under these circumstances ESD clamp 21 may shunt, for example, 20-30 milliamps of current, resulting in significantly increased power consumption for no useful purpose.